Since the introduction of VHDL in 1987, the usage of VHDL for designing complex digital designs has become a commodity. This training day is meant for designers, who have been working with VHDL for some time. During the day, the basic knowledge will be refreshed and a number of less known aspects of VHDL will be discussed.

About a week before the start of the training, you will receive an e-mail with a simple problem. About 2 days before the training, you have to send your solution to the trainer. Your solution will be discussed during the training. 

Subjects

- Going deeper into VHDL (for simulation and synthesis, a.o.:
   o Simulation model
   o Waveforms, transactions 
   o Delay mechanisms 
   o File IO (formatted and text)
   o Overloading, qualification 
   o Impure/pure functions
 
- Fixed point and floating point package
In many applications floating point have been used. In VHDL 2008, VHDL has been provided with packages. With this packages, you can work more easy with this representation. In this training day, the packages which are compatible with VHDL 93, and therefore supported by many synthesis software tools, will be discussed.

The training will be given by Bert Molenkamp, teacher of the faculty Electrical engineering, Mathematics and Information Technology at the University of Twente. He is a VHDL trainer at Transfer since 1989.

Target group

De cursus is suitable for those who work for some time with VHDL. For those, who want to start with VHDL, this training is not very suitable and we advise the more extensive “Fundamentals & Synthesis of VHDL” training.