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Fundamentals of VHDL
Since the introduction of VHDL (VHSIC Hardware Description Language) in 1987, the usage of VHDL for designing complex digital designs has become a commodity. During this 3-days training, with a mixture of theory and practice. the trainee will get sufficient knowledge to understand VHDL descriptions and write VHDL him or herselve. With this training, a good fundament will be created for the usage of VHDL.
When attending this training you will receive a Nanoboard 3000, wit a value of € 300,00, for free. The Nanoboard comes with an Altium Designer Soft Design license valid for one year. This action can not be combined with other (discount) actions.
The training has been given by Bert Molenkamp, teacher of the faculty Electrical Engineering, Mathematics and Information Technology of the University of Twente. He is a VHDL trainer at Transfer since 1989.
Subjects
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VHDL aspects, a.o.:
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Entity, architecture, package, package body and configuration
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Signals, variables
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Concurrent statements
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Sequentiel statements
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Types and subtypes, a.o. std_logic, std_logic_vector
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Functions, procedures
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Overloading
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Generic descriptions
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Simulation model and the effects for synthesis.
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The IEEE packages numeric_std en numeric_bit
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Types signed and unsigned wit predefined operators.
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(Tool independent) synthesis of VHDL, a.o.:
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Combinatorics
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Flipflops, latches
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Backannotation with VITAL
Target group
The training is suitable for designers of digital systems.
Besides basic knowledge of digital technique, experience with a program language is preferred.
3 days
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