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Advanced VHDL

Since the introduction of VHDL (VHSIC Hardware Description Language) in 1987, the usage of VHDL for designing complex digital designs has become a commodity. The advanced VHDL training is meant for designers who work some time with VHDL (designers, but also for engineers who describe test environments). During the training, where theory and practice will vary, the base knowledge will be refreshed and afterwards the less known aspects of VHDL will be considered. Trainees will work on their own case. For this case, alternative descriptions will be discussed about the pro's and con's for simulation and synthesis.


Subjects
  
  • Intensification in VHDL (simulation and synthesis), a.o.:  
    • Simulation model
       
    • Waveforms, transactions, guarded signals (bus, register), (disconnection of) drivers
       
    • Delay mechanisms
       
    • File IO (formatted and text)
       
    • Overloading, qualification
       
    • Protected types, shared variable
       
    • Resolution function
       
    • Impure/pure functions
       
    • Implicit signals
       
  • Introduction Verilog. Often a VHDL user will get in contact with Verilog, e.g. when a synthesis tool generates Verilog output. Also co-simulation of VHDL and Verilog occurs.
  • VITAL (VHDL Initiative Towards ASIC Libraries) enables post simulations with a VHDL simulator, with the 'real' delays of hardware. This enables automatic control for timing constraints. Although it was intentionally meant for ASIC's, it is now a commodity for FPGA's.
  • PSL (Property Specification Language). With the increasing complexity of designs, the need for different verification methods increases. For the hardware description languages, there has been chosen for PSL; an IEEE standard. Nowadays, a lot of VHDL simulators support (embedded) PSL.
  • Choices have been made to give the training to a relatively small group of students. This give the ability to change the training on the fly. For instance, some more attention can be given to :
        - VHDL-AMS Analog Mixed Signal). A superset of VHD, which enables
          the creation of analog models. This has been used in the automotive
          industry!
        - State machines (part of ‘Fundamentals & Synthesis training’).
        - Numeric_std (part of ‘Fundamentals & Synthesis training’).

The training has been given by Bert Molenkamp, teacher of the faculty Elektrotechniek, Wiskunde and Informatica of the Universiteit Twente. He is a VHDL trainer at Transfer since 1989.
  
 
Target group
 
The training is very suitable for those who have worked some time with VHDL (as a designer, but also for test engineers who describe test environments).
 
The training is less suitable for the beginning VHDL user. For them, the training ‘Fundamentals & Synthesis of VHDL’ would be better.
 
Duration 
 
2 days
 
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