Advanced Verification
Over the last years, verification has become more and more important. Sometimes over 70% of the development time is spent in verification. The question is: "When is verification finished?", or, rather: "When is the design sufficiently verified?" Without a verification methodology in place that allows to quantify the progress of the verification process, it is impossible to answer this question.
The Advanced Verification Methodology training focusses on the key technologies that implement a complete verification technology as shown in the following figure:
Assertion based verification
Constrained random tests
Language neutral: SVA, PSL
Testbench automation
Functional coverage
HW/SW co-verification
Lanuage: Use of SCV and System Verilog
Writing of a test plan
Target group
TBS
Duration
3 days
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